1. Field of the Invention
This invention relates to sense amplifiers for programmable logic devices and reading of non-volatile memory cells.
2. Description of Related Art
Programmable logic devices (PLDs) are user programmable devices which perform logical operations as required by a particular application of the PLD. FIG. 1 shows a conventional PLD 1 which generates product terms PT1 to PTM on output nodes 33. Product terms PT1 to PTM have values which are programmable logical combinations of input terms I1 to IK asserted on lines 11 of a PLD array 10. A user selects the logical combination for each product term PT1 to PTM by programming a corresponding column of PLD cells C11 . . . C1N to CM1 . . . CMN.
PLD cells C11 to CMN are conventional non-volatile memory cells such as EPROM cells, EEPROM cells, or Flash EPROM cells. Each PLD cell C11 to CMN has a programmed and an unprogrammed state indicated by whether the threshold voltage of the cell is high or low. Each of input terms I1 to IK and I1 to IK is either high or low (logical value 1 or 0 respectively) and is applied to the gates, either the control gates of single transistor cells or the switching gates of multi-transistor cells, of PLD cells in a corresponding one of rows C11 . . . CM1 to C1N . . . CMN. If an input term on a gate of a cell is high and the cell is unprogrammed, the cell conducts. Otherwise, the cell does not conduct.
A sense amplifier 30 generates product term PT1 by sensing if any of cells C11 to C1N conducts when a particular set of input terms I1 to IK is applied. If none of cells C11 to C1N conducts, a transistor 22 and a cascoding device 26 pull the voltage on a bit line 14 up to about 2 volts. Cascoding device 26 is an N-channel transistor having a drain connected through P-channel transistor 22 to a supply voltage Vcc. A gate of cascoding device 26 is coupled to a reference voltage PLDREF. When the voltage on bit line 14 reaches voltage PLDREF minus the threshold voltage of cascoding device 26, cascoding device 26 shuts off and stops pulling up the voltage on bit line 14. The voltage on bit line 14 is selected to protect cells C11 to C1N from a read disturb of the threshold voltages.
P-channel transistor 22 has a source coupled to supply voltage Vcc and a gate and a drain coupled together and to the drain of cascoding device 26. If none of cells C11 to C1N conduct, the gate of transistor 22 remains at about supply voltage Vcc minus the threshold voltage of transistor 22 so that transistor 22 is off. Sense amplifier 30 contains a P-channel transistor 31 and an N-channel transistor 32 having gates coupled through a line 24 to the gate of P-channel transistor 22. When there is no current through any of PLD cells C11 to C1N, the voltage on line 24 shuts off transistor 31 and turns on transistor 32, and transistor 32 pulls product term PT1 to low (approximately ground potential).
If at least one of cells C11 to C1N conducts, the conducting cell draws a current which pulls bit line 14 down. The dropping voltage is amplified by cascoding device 26 to cause an amplified signal on the gates of transistors 31 and 32 in sense amplifier 30. When the amplified signal applied to the gates of transistors 31 and 32 drops to a trip point, transistor 32 turns off, and transistor 31 turns on and pulls product term PT1 up to about supply voltage Vcc. An N-channel transistor 20 between the sources of cells C11 to C1N and ground has a gate coupled to bit line 14 and shuts off current through cells C11 to C1N if the voltage on bit line 14 drops to the threshold voltage of transistor 20. This keeps bit line 14 from reaching ground potential and speeds up recharging of bit line 14 if input terms I1 to IK change and stop all of cells C11 to C1N from conducting.
The rate at which bit line 14 is pulled down depends upon the saturation current through the conducting PLD cell or cells and the strength of pull-up transistor 22. Transistor 22 must supply less current than the minimum saturation current of a single one of cells C11 to C1N in order for bit line 14 to be pulled down. However, when input terms I1 to IK change from a state where at least one of cells C11 to C1N conduct to a state where none of cells C11 to C1N conduct, transistor 22 provides current that pulls bit line 14 up to a trip point where sense amplifier 30 pulls product term PT1 low. If transistor 22 is made weaker, the time to pull up the voltage of bit line 14 is longer, and the read time required for sense amplifier 30 to correctly generate product term PT1 is longer.
To improve the life of programming in cells C11 to CMN, a regulated supply voltage Vccr (not shown) may be applied to the control gate of the cells. Typically, in a 5-volt application, PLD cells C11 to CMN have a threshold voltage of about 1.5 volts in the unprogrammed state and an initial threshold voltage of about 6.5 volts in a programmed state, and regulated voltage Vccr is between about 3 and 4.5 volts. Using regulated voltage Vccr prolongs the life of the programming of cells C11 to CMN because even if charge leaks from a programmed cell and lowers the threshold voltage of a programmed cell from 6.5 volts to 5.5 volts, regulated voltage Vccr is lower than the threshold voltage and keep programmed cells off. In contrast, industry standard voltage supplies permit a 10% fluctuation in supply voltage Vcc. For a supply voltage Vcc which is 5.0.+-.0.5 volts, fluctuations in the supply voltage can apply 5.5 volts to the control gate which causes cells having threshold voltage around 5.5 volts to conduct and causes PLD 1 to fail.
A problem with using regulated voltage Vccr is that the saturation current of cells C11 to C1N drops when the control gate voltage is lowered. This reduces the ability of a cell to pull down bit line 14. The problem is made worse when supply voltage Vcc is high and increases the strength pull-up strength of transistor 22 relative to the fixed saturation current of cells C11 to C1N. This requires that transistor 22 be made so small and weak that the read time (time to pull-up bit line 14) of PLD 1 is unacceptably long. If transistor 22 is not made this small, a single cell C11 to C1N may have a saturation current which is too small to pull down bit line 14 and trip sense amplifier 30, and this would cause PLD 1 to fail. Accordingly, a PLD sense amplifier system is needed which can function with an acceptable read time even when a regulated voltage is applied to cells of the PLD.